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1 ? fn6228.1 ISL55110, isl55111 dual, high speed mosfet driver the ISL55110 and isl55111 are dual high speed mosfet drivers intended for applications requiring accurate pulse generation and buffering. target applications include ultrasound, ccd imaging, au tomotive piezoelectric distance sensing and clock generation circuits. with a wide output voltage range and low on resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew as required in large ccd array imaging applications. the ISL55110 and isl55111 are compatible with 3.3v and 5v logic families and incorpor ate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. the ISL55110 has a pair of in-phase drivers while the isl55111 has two drivers operating in antiphase. both inputs of the device have independent inputs to allow external time phasing if required. the ISL55110 has a power down mode for low power consumption during equipment standby times, making it ideal for portable products. the ISL55110 and isl55111 are available in 16 ld exposed pad qfn packaging and 8 ld tssop. both devices are specified for operation over the full -40c to +85c temperature range. functional block diagram features ? 5v to 12v pulse magnitude ? high current drive 3.5a ? 6ns minimum pulse width ? 1.5ns rise and fall times, 100pf load time ?low skew ? 3.3v and 5v logic compatible ? in-phase and anti-phase outputs ? small qfn and tssop packaging ? low quiescent current ? pb-free plus anneal available (rohs compliant) applications ? ultrasound mosfet driver ? ccd array horizontal driver ? automotive piezo dr iver applications ? clock driver circuits isll55110 and isl55111 dual driver vh oa ob in-a o o o o o in-b o o gnd o power down o vdd o hiz-qfn* * hiz available in qfn package only * isl55111 in-b is inverting * ordering information part number part marking temp. range (c) package pkg. dwg. # ISL55110irz* (note) 55 110irz -40 to +85 16 ld qfn (pb-free) l16.4x4a ISL55110ivz* (note) 55110 ivz -40 to +85 8 ld tssop (pb-free) m8.173 isl55111irz* (note) 55 11irz -40 to +85 16 ld qfn (pb-free) l16.4x4a isl55111ivz* (note) 55111 ivz -40 to +85 8 ld tssop (pb-free) m8.173 *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 21, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2003, 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6228.1 march 21, 2007 pinout ISL55110 (16 ld qfn) top view isl55111 (16 ld qfn) top view ISL55110 (8 ld tssop) top view isl55111 (8 ld tssop) top view 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc nc nc nc 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd pin descriptions pin function vdd logic power. vh driver high rail supply gnd ground, return for both vh rail and vdd logic supply. pd power down. active logic high places part in power down mode. enable qfn packages only. provides high speed logic hiz contro l of driver outputs while leaving device logic power on. in-a logic level input that drives oa to vh rail or ground. not inverted. in-b, inb logic level input that drive ob to vh rail or ground. not inverted on ISL55110, inverted on isl55111. oa driver output related to in-a. ob driver output related to in-b. ISL55110, isl55111 nc nc nc
3 fn6228.1 march 21, 2007 absolute maxi mum ratings (t a = +25c) thermal information vh+ to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0v vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v vin_a, vin_v, pdn, enable . . . . . . . . (gnd-0.5v) to (vdd+0.5v) oa, ob. . . . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd-0.5) to (vh+0.5v) maximum peak output current . . . . . . . . . . . . . . . . . . . . . . (300ma) esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance ja (c/w) 16 ld (4x4) qfn package (note 2) . . . . . . . . . . . . . 45 8 ld tssop package (note 1) . . . . . . . . . . . . . . . . 140 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a notes: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. recommended operating conditions parameter description conditions min typ max unit vh driver supply voltage 5 12 13.2 v vdd logic supply voltage 2.7 5.5 v t a ambient temperature -40 +85 c t j junction temperature +150 c dc electrical specifications vh = +12v, vdd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. parameter description test conditions min typ max units logic characteristics vix_lh logic input threshold - low to high l ih = 1a: vin_a, vin_b 1.32 1.42 1.52 v vix_hl logic input threshold - high to low l il = 1a: vin_a, vin_b 1.12 1.22 1.32 v vhys logic input hysteresis vin_a,vin_b 0.2 v vih logic input high threshold pdn 2.0 vdd v vil logic input low threshold pdn 0 0.8 v vih logic input high threshold enable - qfn only 2.0 vdd v vil logic input low threshold enable - qfn only 0 0.8 v iix_h input current logic high vin_a,vin_b = vdd 10 20 na iix_l input current logic low vin_a, vin_b = 0v 10 20 na ii_h input current logic high pdn = vdd 10 20 na ii_l input current logic low pdn = 0v 10 15 na ii_h input current logic high enable = vdd - qfn only 12 ma ii_l input current logic low enable = 0v - qfn only -25 na ISL55110, isl55111
4 fn6228.1 march 21, 2007 driver characteristics r ds driver output resistance oa, ob 3 6 i dc driver output dc current (>2s) 100 ma i ac peak output current design intent verified via simulation. 3.5 a voh to vol driver output swing range vh voltage to ground 3 13.2 v supply currents i dd logic supply quiescent current pdn = low 4.0 6.0 ma i dd-pdn logic supply power down current pdn = high 12 a ih driver supply quiescent current pdn = low, no resistive load d out 15 a ih_pdn driver supply power down current pdn = high 1 a dc electrical specifications (continued) vh = +12v, vdd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. parameter description test conditions min typ max units ac electrical specifications vh = +12v, vdd = +3.6, t a = +25c, unless otherwise specified. parameter description test conditions min typ max units switching characteristics t r, t f driver rise/fall time oa,ob: cl = no load 10% to 90%, voh-vol = 12v 10% to 90%, voh-vol = 10v 1.0 1.0 ns ns t r, t f driver rise/fall time oa, ob cl = 1nf 10% to 90%, voh-vol = 12v 6.7 ns tpdr input to output propagation delay figure 2, load 100pf/1k 12.0 ns tpdf input to output propagation delay 9.3 ns tpdr input to output propagation delay figure 2, load 220pf 12.5 ns tpdf input to output propagation delay 10.2 ns tpdr input to output propagation delay figure 2, load 330pf 12.9 ns tpdf input to output propagation delay 10.6 ns tpdr input to output propagation delay figure 2, load 680pf 14.1 ns tpdf input to output propagation delay 12.1 ns tskewr channel to channel tpdr spread with same loads both channels figure 2, all loads <0.5 ns tskewf channel to channel tpdf spread with same loads both channels. figure 2, all loads <0.5 ns fmax maximum operating frequency 70 mhz tmin minimum pulse width 6 ns pden* power-down to power-on time 0.7 1.0 ms pddis* power-on to power-down time 1.4 1.6 ms ten* enable to enable time (hiz off) 0.3 0.7 ms tdis* enable to enable time (hiz on) 1.4 1.6 ms ISL55110, isl55111
5 fn6228.1 march 21, 2007 figure 1. test circuit rise (t r )/fall(t f ) thresholds figure 2. test circuit propagation tpd delay ISL55110 input input rise and fall times 2ns c l 4.7 f 0.1 f + output vh = 12v 50% 50% 50% 50% tpdr tpdf 0.4v 12v input +3v 0v output oa and ob isls55110 in-x in output oa isls55111 50% 50% 12v 0v output ob isls55111 t skew r = tpdr chn1 - tpdr chn2 ISL55110 input input rise and fall times 2ns c l 4.7 f 0.1 f + output vh = 12v 10% 10% 90% t f 90% t r 0.4v 12v input +3v 0v output inx in ISL55110, isl55111
6 fn6228.1 march 21, 2007 typical performance curves (see typical performance curves discussion) figure 3. driver ron vs vh source resistance figure 4. driver ron vs vh sink resistance figure 5. ron vs vdd source resistance figure 6. ron vs vdd sink resistance figure 7. idd vs vdd quiescent current figure 8. idd vs vh @ 50mhz (no load) 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 vh, drive rail (v) +85c +25c -40c ron vdd 3.6v -50ma 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 vh, drive rail (v) +85 c +25 c -40 c ron +50ma vdd 3.6v 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 vdd (v) vh 5.0v ron ( ) 50ma vh 12.0v 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 vdd (v) vh 12.0v ron ( ) 50ma vh 5.0v 4.0 3.8 3.6 3.4 3.2 3.0 2.5 3.5 4.5 5.5 vdd (v) idd (ma) vh 5v and 12v 10 9 8 7 6 5 4 3 2 1 0 4812 idd (ma) vdd 3.6v vh, drive rail (v) ISL55110, isl55111
7 fn6228.1 march 21, 2007 figure 9. quiescent ih vs vh figure 10. ih vs vh @ 50mhz (no load) figure 11. idd vs frequency (dual channel, no load)l figure 12. ih vs frequency (dual channel, no load) figure 13. vih logic thresholds figure 14. vil logic thresholds typical performance curves (continued) (see typical perform ance curves discussion) 100 90 80 70 60 50 40 30 20 10 0 4812 vh, drive rail (v) ih (a) vdd 3.6v 200 180 160 140 120 100 80 60 40 20 0 4812 vh, drive rail (v) ih (ma) vdd 3.6v 15.0 13.5 12.0 10.5 9.00 7.50 6.00 4.50 2.00 0.50 0.00 50m 66m 100m 124m 128m toggle frequency in hz idd (ma) vh 5.0v vdd 3.6v 200 180 160 140 120 100 80 60 40 20 0 50m 100m 128m toggle frequency in hz 66m 124m ih (ma) vh 5.0v vdd 3.6v 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 vdd (v) -40c +85c logic (v) 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 vdd (v) logic (v) -40c +85c ISL55110, isl55111
8 fn6228.1 march 21, 2007 figure 15. t r vs temperature figure 16. t f vs temperature figure 17. tpd r vs temperature figure 18. tpd f vs temperature figure 19. t r vs vdd figure 20. t f vs vdd typical performance curves (continued) (see typical perform ance curves discussion) 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 + 85 package temp (c) rise time (ns) 1000pf 680pf 330pf 100pf/1k vh 12.0v vdd 3.6v 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 +85 package temp (c) fall time (ns) 100pf/1k 680pf 330pf 1000pf vdd 3.6v vh 12.0v 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) 100pf/1k 330pf 680pf 1000pf vh 12.0v vdd 3.6v vh 12.0v vdd 3.6v 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) 100pf/1k 330pf 680pf 1000pf 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 vdd (v) rise time (ns) vh 12.0v 4.5 1000pf 680pf 330pf 100pf/1k 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 vdd (v) fall time (ns) vh 12.0v 4.5 1000pf 680pf 330pf 100pf/1k ISL55110, isl55111
9 fn6228.1 march 21, 2007 figure 21. t r vs vh figure 22. t f vs vh figure 23. tpd r vs vdd figure 24. tpd f vs vdd figure 25. tpd r vs vh figure 26. tpd f vs vh typical performance curves (continued) (see typical perform ance curves discussion) 12.0 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 36 12 vh (v) rise time (ns) vdd 3.3v 9 1000pf 680pf 330pf 100pf/1k 36 12 vdd (v) fall time (ns) vdd 3.3v 9 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 12.0 1000pf 680pf 330pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 vdd (v) propagation delay (ns) vh 12.0v 4.5 1000pf 680pf 330pf 100pf/1k 5.5 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 5.5 vdd (v) propagation delay (ns) vh 12.0v 4.5 1000pf 680pf 330pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 vh (v) propagation delay (ns) vdd 3.3v 9 1000pf 680pf 330pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 vh (v) propagation delay (ns) vdd 3.3v 9 1000pf 680pf 330pf 100pf/1k ISL55110, isl55111
10 fn6228.1 march 21, 2007 figure 27. tskew r vs temperature figure 28. tskew f vs temperature figure 29. tskew r vs vdd figure 30. tskew f vs vdd figure 31. tskew r vs vh figure 32. tskew f vs vh typical performance curves (continued) (see typical perform ance curves discussion) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewr (ns) 680pf 330pf vh 12.0v vdd 3.6v 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewf (ns) 680pf and 330pf vh 12.0v vdd 3.6v 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 vdd (v) skew (ns) vh 12.0v 4.5 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 vdd (v) skew (ns) vh 12.0v 4.5 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 vdd (v) skew (ns) vdd 3.3v 9 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 vdd (v) skew (ns) vdd 3.3v 9 680pf 330pf ISL55110, isl55111
11 fn6228.1 march 21, 2007 typical performance curves discussion ron ron source tested by placing device in constant drive high condition and connecting -50ma constant current source to the driver output. voltage drop measured from vh to driver output for ron calculations. ron sink tested by placing device in constant driver low condition and connecting a +50ma constant current source. voltage drop from driver out to ground measured for ron calculations. dynamic tests all dynamic tests are conduc ted with ISL55110, isl55111 evaluation board(s). driver loads are soldered to the evaluation board. measurements are collected with p6245 active fet probes and tds5104 oscilloscope. pulse stimulus is provided by hp8131 pulse generator. the ISL55110, isl55111 eval uation boards provide test point fields for leadless connection to either an active fet probe or differential probe. tp-in fields are used for monitoring pulse input stimulus. tp-oa/b monitor driver output waveforms. c6 and c7 are the usual placement for driver loads. r3 and r4 are not populated and provided for user-specified, more complex load characterization. pin skew pin skew measurements are based on the difference in propagation delay of the two channels. measurements are made on each channel from the 50% point on the stimulus point to the 50% point on the dr iver output. the difference in the propagation delay for channel a and channel b is considered to be skew. both rising propagation delay and falling propagation delay are measured and reports as tskewr and tskewf. 50mhz tests 50mhz tests reported as no load actually include evaluation board parasitics and a single tek 6545 fet probe. however no driver load components are installed, c6 through c9 and r3 through r6 are not populated. general most dynamic measurements ar e presented in three ways. first over temperature with a v dd of 3.6v and vh of 12.0v. second, at ambient with vh set to 12v and vdd data points of 2.5v, 3.5v, 4.5v and 5.50v. third, the ambient tests are repeated with vdd of 3.3v and vh data points of 3v, 6v, 9v and 12v. ISL55110, isl55111
12 fn6228.1 march 21, 2007 detailed description the ISL55110 and isl55111 are dual high speed mosfet drivers intended for applicati ons requiring accurate pulse generation and buffering. target applications include ultrasound, ccd imaging, au tomotive piezoelectric distance sensing and clock generation circuits. with a wide output voltage range and low on resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew as required in large ccd array imaging applications. the ISL55110 and isl55111 are compatible with 3.3v and 5v logic families and incorpor ate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. the ISL55110 has a pair of in-phase drivers while the isl55111 two drivers operating in antiphase. both inputs of the device have independent inputs to allow external time phasing if required. in addition to power mos drivers, the ISL55110, isl55111 is well suited for other applications such as bus, control signal, and clock drivers on large memory of microprocessor boards, where the load capacitance is large and low propagation delays are required. other potentia l applications include peripheral power drivers and charge-pump voltage inverters. input stage the input stage is a high impedance input with rise/fall hysteresis. this means that the inputs will be directly compatible with both ttl and lower voltage logic over the entire vdd range. the user should treat the inputs as high speed pins and keep rise and fall times to <2ns. output stage the ISL55110, isl55111 ou tput is a high-power cmos driver, swinging between ground and vh. at vh = 12v, the output impedance of the inve rter is typically 3.0 . the high peak current capability of the ISL55110, isl55111 enables it to drive a 330pf load to 12v with a rise time of <3.0ns over the full temperature range. the output swing of the ISL55110, isl55111 comes within < 30mv of the vh and ground rails. application notes although the ISL55110, isl55111 is simply a dual level- shifting driver, there are several areas to which careful attention must be paid. grounding since the input and the high current output current paths both include the ground pin, it is very important to minimize and common impedance in the ground return. since the isl55111 has one inverting input, any common impedance will generate negative feedback, and may degrade the delay, rise and fall times. use a ground plane if possible, or use separate ground returns for the input and output circuits. to minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the ISL55110, isl55111 as is possible. bypassing the rapid charging and discharging of the load capacitance requires very high current spik es from the power supplies. a parallel combination of capacitors that has a low impedance over a wide frequency range should be used. a 4.7 f tantalum capacitor in parallel with a low inductance 0.1 f capacitor is usually sufficient bypassing. output damping ringing is a common problem in any circuit with very fast rise or fall times. such ringing will be aggravated by long inductive lines with capacitive loads. te chniques to reduce ringing include: 1. reduce inductance by making printed circuit board traces as short as possible. 2. reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. 3. use small damping resistor in series with the output of the ISL55110, isl55111. although this reduces ringing, it will also slightly increase the rise and fall times. 4. use good by passing techniques to prevent supply volt- age ringing. power dissipation calculation the power dissipation equation has three components: quiescent power dissipation, power dissipation due to internal parasitics and power dissipation because of the load capacitor. power dissipation due to internal parasitics is usually the most difficult to accurately quantitize. this is primarily due to crow-bar current which is a product of both the high and low drivers conducting effectively at the same time during driver transitions. design goals always target the minimum time for this condition to exist. given that how often this occurs is a product of frequency, crowbar effects can be characterized as internal capacitance. lab tests are conducted with driver outputs disconnected from any load. with design verification packaging, bond wires are removed to aid in the characterization process. base on laboratory tests and simulation correlation of those results, the following equation defines the ISL55110, isl55111 power dissipation per channel: p = vdd*3.3e-3 + 10pf*vdd^2*f + 135pf*vh^2*f + cl*vh^2*f (watts/channel) ISL55110, isl55111
13 fn6228.1 march 21, 2007 where: 1. 3.3ma is the quiescent cu rrent from the vdd. this forms a small portion of the total calculation. when figuring two channel power consumption, only include this current once. 2. 10pf is the approxim ate parasitic capacitor (inverters, etc.), which the vdd drives 3. 135pf is the approximate parasitic at the dout and its buffers. this includes the effect of the crow-bar current. 4. cl is the load capacitor being driven power dissipation discussion specifying continuous pulse rates, driver loads and driver level amplitudes are key in determining power supply requirements as well as dissipation / cooling necessities. driver output patterns also impact these needs. the faster the pin activity, the greater the need to supply current and remove heat. as detailed in the power dissipation calculation section, power dissipation of the device is calculated by taking the dc current of the vdd (logic) and vh current (driver rail) times the respective voltages and adding the product of both calculations. the average dc current measurements of idd and ih should be done while running the device with the planned vdd and vh levels and driving the required pulse activity of both channels at the desired operating frequency and driver loads. therefore the user must address power dissipation relative to the planned operating conditions. even with a device mounted per note 1 or 2 under thermal information, given the high speed pulse rate and amplitude capability of the ISL55110, isl55111, it is possible to exceed the +150c ?absolute-maximum junction temp erature?. therefore, it is important to calculate the maximum junction temperature for the application to determine if operating conditions need to be modified for the device to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads. power also depends on number of channels changing state and frequency of operation. the extent of continuous active pulse generation will greatly effect dissipation requirements. the user should evaluate various heat sink/cooling options in order to control the ambi ent temperature part of the equation. this is especially true if the user?s applications require continuous, high speed operation. a review of the theta-j ratings of the tssop and qfn package clearly show the qfn package to have better thermal characteristics. the reader is cautioned against assuming a calculated level of thermal performance in actual applications. a careful inspection of conditions in your application should be conducted. great care must be taken to ensure die temperature does not exceed 150c absolute maximum thermal limits. important note: the ISL55110, isl55111 qfn package metal plane is used for heat sinking of the device. it is electrically connected to the negative supply potential ground. power supply sequencing the ISL55110, isl55111 references both vdd and the vh driver supplies with respect to ground. therefore apply vdd, then vh. digital inputs should never be open. do not apply slow analog ramps to the inputs. again place decoupling as close to the package as possible for both vdd and especially vh. special loading with most applications the us er will usually have a special load requirement. please contact intersil for evaluation boards or to request a device characterization to your requirements in our lab. p dmax t jmax - t amax ja -------------------------------------------- - = ISL55110, isl55111
14 fn6228.1 march 21, 2007 ISL55110, isl55111 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4a 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggd-10) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 2.30 2.40 2.55 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 2.30 2.40 2.55 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 2 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6228.1 march 21, 2007 ISL55110, isl55111 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m8.173 8 lead thin shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n8 87 0 o 8 o 0 o 8 o - rev. 1 12/00

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